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SP7545
Corporation
SIGNAL PROCESSING EXCELLENCE
12-Bit, Buffered Multiplying DAC
s 1.0 LSB Relative Accuracy Over Temperature s Monotonic to 12-Bits Over Temperature s High Stability, Segmented Architecture s Proprietary, Low TCR Thin-Film Resistor Technology s Operates With +5V to +15V Power Supplies s On-Board, Level-Triggered Latches s 2kVESD Protection on all Digital Inputs
DESCRIPTION... The SP7545 is a low-cost, high stability 12-bit CMOS multiplying DAC with on-board data latches. The SP7545 is constructed using a proprietary low-TCR thin-film process that requires no laser-trimming to achieve 12-bit performance. With no laser-trimming, inherent high stability, and a segmented (decoded) DAC architecture, the SP7545 retains its performance over time and temperature. The SP7545 is available for use in commercial and industrial temperature ranges. It is available in 20-pin plastic DIP and PLCC packages.
VDD [18]
D11 (MSB) [4] D10 [5] D9 [6] D8 [7] D7 [8] D6 [9] D5 [10] D4 [11] D3 [12] AGND [2] D2 [13] D1 [14] D0 (LSB) [15] 12-BIT DAC REGISTER 12-BIT DAC IO1 [1] RFB [20] VREF [19]
GND [3]
Corporation
175
SIGNAL PROCESSING EXCELLENCE
ABSOLUTE MAXIMUM RATINGS
(TA = 25C unless otherwise noted.) These are stress ratings only and functional operation of the device at these or any other above those indicated in the operation sections of the specifications below is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. VDD to GND .................................................................. -0.3V, +17V Digital Input Voltage to GND ................................. -0.3V, VDD+0.3V VREF or VRFB to GND ................................................................ 25V Output Voltage (Pin 1, Pin 2) ................................ -0.3V, VDD+0.3V Power Dissipation (Any Package to +75C) ........................ 450mW Derates above 75C by ...................................................... 6mW/C Dice Junction Temperature ................................................. +150C Storage Temperature ............................................ -65C to +150C Lead Temperature (Soldering, 60 seconds) ........................ +300C
SPECIFICATIONS
(TA=25C; VDD =+5V or +15V as noted; VREF = +10V; IO1 = AGND = GND = 0V; unipolar unless otherwise noted.)
PARAMETER STATIC PERFORMANCE Resolution Integral Non-Linearity -J -K Differential Non-Linearity -J -K Gain Error -J -K
MIN. 12
TYP.
MAX.
UNIT Bits
CONDITIONS
2.0 1.0 4.0 1.0 20 25 10 15 10
LSB LSB LSB LSB LSB LSB LSB LSB nA
Output Leakage Current AC PERFORMANCE CHARACTERISTICS Propagation Delay Current Settling Time Output Capacitance 50 25 Glitch Energy Multiplying Feedthrough Error STABILITY Gain Error TC Integral Non-Linearity TC Differential Non-Linearity TC Power Supply Rejection 250 2.0 0.2 1.0 0.1 0.1 0.002
300 250 2.0 200 200 70 70
ns ns s pF pF pF pF nV-s mV mV
P-P P-P
Note 6 Note 5; 11-bit relative accuracy Note 5; 12-bit relative accuracy Note 7 Note 5; monotonic to 12-bits Note 5; monotonic to 12-bits Note 16 VDD = +5V; Note 5 VDD = +15V VDD = +5V VDD = +15V At I (Pin 1); Note 5 and 17 Output Amplifier HOS-050; Note 10 VDD = +5V; Note 11 VDD = +15V; Note 11 Full scale transition; Note 12 WR, CS = 0V; data inputs V Note 5; data inputs V Data inputs 0V Note 5; data inputs 0V Note 13 Measured at output I ; Note 14 Measured at output I ; Note 15
O1 DD O1 O1
DD
2.0 2.0 1.0 1.0 1.0 1.0 0.01 0.02
ppm/C ppm/C ppm/C ppm/C ppm/C ppm/C %/% %/% K ppm/C Volts
Note 5 Note 5 Note 5
%/0.005% change in power supply voltage
Note 5 Pin 19 to GND Note 5 and 8
REFERENCE INPUT Input Resistance Input Resistance TC Voltage Range
7
10 150
15 25
176
Corporation
SIGNAL PROCESSING EXCELLENCE
SPECIFICATIONS (continued)
(TA=25C; VDD =+5V, VREF = +10V; IO1 = AGND = GND = 0V; unipolar unless otherwise noted.)
PARAMETER DIGITAL INPUTS Logic Levels VIH
MIN.
TYP.
MAX.
UNIT
CONDITIONS
2.4 13.5
VIL
-0.3 -0.3
Input Current Input Capacitance Bits 1--12 WR, CS Coding Unipolar Bipolar POWER REQUIREMENTS Supply Current
VDD 2.4 VDD 13.5 0.8 0.8 1.5 1.5 1.0 10 5 20 Binary Offset Binary 2.0 2.0 0.5
Volts Volts Volts Volts Volts Volts Volts Volts A A pF pF
VDD = +5V VDD = +5V; Note 5 VDD = +15V VDD = +15V; Note 5 VDD = +5V VDD = +5V; Note 5 VDD = +15V VDD = +15V; Note 5 VIN = 0V or VDD Note 5 and 9 VIN = 0; Note 5 and 8
mA mA mA mA
All digital inputs VIL or VIH Note 5; all digital inputs VIL or VIH Note 18 Note 5 and 18
ENVIRONMENTAL AND MECHANICAL Operating Temperature Commercial 0 +70 Industrial -40 +85 Storage Temperature -65 +150 Package 20-pin Plastic DIP 20-pin Plastic LCC
C C C
Notes and Cautions: 1. Do not apply voltages higher than VDD or less than GND potential on any terminal other than VREF or VRFB. 2. The digital inputs are diode-clamp protected against ESD damage. However, permanent damage may occur on unprotected units from high-energy electrostatic fields. Keep units in conductive foam at all times until ready to use. 3. Use proper anti-static handling procedures. 4. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation at or above these specifications is not implied. Exposure to the above maximum rated conditions for extended periods may affect device reliability. 5. From TMIN to TMAX. 6. End-point linearity 7. Differential Non-linearity is the deviation of an output step from the theoretical value of 1 LSB for any two adjacent digital input codes. 8. Guaranteed by design, but not production tested. 9. Logic inputs are MOS gates. IIN typically is less than 1nA @ 25C. 10. AC performance characteristics are included for design guidance only and are subject to sample testing only. 11. RL = 100, CEXT = 13pF; all data inputs 0V to VDD or VDD to 0V; from 50% digital input change to 90% of final analog output. 12. Settling to 0.01% FSR (strobed); all data inputs 0V to VDD or VDD to 0V. 13. VREF = 0V, DAC register alternatively loaded with all 0's and all 1's. 14. VREF = 20VP-P; F = 10kHz sinewave. 15. VREF = 20VP-P; F = 1kHz sinewave. 16. Measured using internal feedback resistor with DAC loaded with all 1's. 17. All digital inputs = 0V. 18. All digital inputs 0V or VDD.
Corporation
177
SIGNAL PROCESSING EXCELLENCE
ORDERING INFORMATION
Model Integral Linearity Package 0C to +70C Operating Temperature SP7545JCN ............................................................................ 2LSB .................................................................................. 20-pin, 0.3" Plastic DIP SP7545JCL ............................................................................. 2LSB ................................................................................................... 20-pin PLCC SP7545KCN ............................................................................ 1LSB .................................................................................. 20-pin, 0.3" Plastic DIP SP7545KCL ............................................................................ 1LSB ................................................................................................... 20-pin PLCC -40C to +85C Operating Temperature SP7545JIN .............................................................................. SP7545JIL .............................................................................. SP7545KIN ............................................................................. SP7545KIL ..............................................................................
2LSB 2LSB 1LSB 1LSB
.................................................................................. 20-pin, 0.3" Plastic DIP ................................................................................................... 20-pin PLCC .................................................................................. 20-pin, 0.3" Plastic DIP ................................................................................................... 20-pin PLCC
180
Corporation
SIGNAL PROCESSING EXCELLENCE

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